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| AS3502 Austria Mikro Systeme International AG 13-BIT LINEAR FEATURE CODEC WITH ANALOGUE FRONTEND General Description AS3502 is a high performance 13-bit linear feature Codec/Filter with 8 kHz sampling rate specifically tailored to implement all analogue frontend functions of battery powered digital terminals. It includes a programmable analogue interfaces for handset and handsfree operation with a minimum amount of external components. The Codec function of AS3502 uses Sigma-Delta () modulation conversion techniques with 2nd order modulators and an over sampling rate of 128 for excellent signal to noise performance. The AS3502 exceeds all CCITT G712 recommendations and the European ETSI prETS 300085 recommendations. Digital gain setting stages for transmit and receive allow to compensate for transducer tolerances and to set up a handsfree function under software control. A programmable tone generator allows to generate DTMF/Call-Progress Tones and alert sounds required in digital terminals. All programmable functions of AS3502 are controlled by a 4-wire serial control port that easily interfaces to any popular micro controller. The interface to the digital world is accomplished by a serial PCM interface that supports 16-bit linear format or 8-bit A-Law format for both non-delayed and delayed frame synchronzation modes. Key Features q q q q q q q q q q q q q q q q 13-Bit Linear Sigma Delta Codec with Filters Exceeding ETSI prETS30085 and G712 . Single Rail 3.0 V ~5.5 V Power Supply. Typical Power Dissipation of 30 mW at 3 V. Two Low Noise Microphone Inputs with Internal Gain Adjust (+16 / +46 dB). 150 Push/Pull Earpiece Driver with Internal Gain Adjust (-12 / +6 dB). 50 Loudspeaker Amplifier with up to 50 mW Output Power. Push/ Pull Output Driver for Tone Ringer. On Chip Electret Microphone Voltage Source. Digital Transmit Gain Setting (-38 / +10 dB). Digital Receive Gain Setting ( -42 / +6 dB). Digital Sidetone Control Function ( 0 / -48 dB). Programmable Call Progress Tone/ DTMF / Ring Tone Generator. Analogue and Digital Loopback Modes. 16-Bit Linear / 8-Bit A-Law Switchable Serial PCM Interface with Non Delayed and Delayed Timing Modes. 4-Wire Serial Control Interface. Packaged in SOIC-28, TQFP-64. Block Diagramme MIC2+ MIC2MIC1+ MIC1VOICE AAF AGX + 16/46 dB SINE VREF AGR -12/+6 dB DGR Lin/A- AS3502 DGX Lin/A- ADC TONE LOOP Decimation Filter BPF dB -38/+10 Comp. PCM PCM TX TX TXD TXS 30K F1-F3, V1-V3 + VREF + Freq. Gen. SQ. S1, S2 CP, CP RP, RO SG DC Seq. Caden. Rep. dB 0/-48 Contr. MCLK SCLK EP+ LPF EPSPK+ +3dB SPK- + DAC + V2 LOOP Interpolation Filter LPF dB -42/+6 + Exp. PCM PCM RX TX RXS RXD DAC AGND POR Serial Control GND DV DD TRO- TRO+ AV DD CAP AVSS POR CS SCL SDI SDO REV. M Page 1 September 1998 AS3502 Pinout Diagramme AV DD CAP MIC1+ MIC1MIC2MIC2+ N.C. V REF DV DD POR CS SCL SDI SDO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 SPKMIC1+ MIC1SPK+ 53 AVDD CAP EP49 45 SPK+ AV SS EPEP+ TROTRO+ GNDD MCLK SCLK TXD TXS RXS RXD DVDD PO R CS 12 14 16 63 61 59 57 55 MIC2MIC2+ V REF 1 3 6 EP+ TRO TRO + G NDD MCLK 51 30 TXD AVSS SPK- A S3502 42 40 38 34 18 20 22 24 26 28 28 Pin SOIC 64 pin TQFP Pin Description Pin # 1 2 Name AVDD CAP Type SI AO Function Analogue Positive Supply Voltage Input Filter Capacitor Output This pin requires to be connected to an external blocking capacitor of app. 47F and is internally connected to the potential divider of the analogue ground generation circuit. Differential Microphone 1 Inputs These two pins are differential inputs to the analogue input multiplexer of the gain programmable microphone amplifier with an input impedance of approx. 60 k. Differential Microphone 2 Inputs These two pins are differential inputs to the analogue input multiplexer of the gain programmable microphone amplifier with an input impedance of approx. 60 k. Microphone Reference Voltage Output This pin provides a stabilized reference voltage for an electret microphone of approx. 2V. Digital Positive Supply Voltage Input 3 4 5 6 7 8 MIC1MIC1+ MIC2MIC2+ N.C. VREF AI AI AI AI AO 9 DVDD SI REV. M Page 2 SCLK SCL RXD RXS SDO TXS SDI 32 September 1998 AS3502 Pin Description (continued) Pin # 10 Name POR Type DI Function Power On Reset Input An active Low signal on this pin starts the system initialization. All internal registers are set to their default values and the serial interface will be reinitialized and the chip will enter power down mode. Serial Control Chip Select Input An active Low signal on this pin enables serial data transfers via SDI and SDO. Serial Control Clock Input This pin acts as shift clock signal input for serial control data transfer via SDI and SDO when CS is active Low and may be asynchronous to all other clock signals. Serial Control Data Input This input samples control data bits on the rising edges of the serial clock SCL when CS is active Low. Depending on the type of transfer 8 or 16 bits are shifted in. Serial Control Data Output This output shifts out control/status data with the falling edge of SCL when CS is active Low. Receive PCM Data Input This input samples PCM data bits on the falling edges of the serial clock SCLK following a rising edge on the receive strobe signal. After the time when all data bits have been shifted into the receive shift register all bits are latched into the receive latch for digital to analogue conversion. Receive PCM Strobe Input The signal on this input initiates shifting of serial data into the receive shift register. It must be synchronized with SCLK. The clock rate is typically 8 kHz. The signal width determines whether short strobe or long strobe mode is used: A pulse width of one to two shift clock periods selects short strobe mode. (For further information see PCM Timing Diagramme ). The strobe signal does not need to be active throughout the transmission period since an internal bit counter generates the necessary timing for 8 or16 bit periods depending on the selected output format for serial PCM reception. Transmit PCM Strobe Input This signal on this input initiates shifting of serial data out of the transmit shift register. It must be synchronized with SCLK. The clock rate is typically 8 kHz. The signal width determines whether short strobe or long strobe mode is used: A pulse width of one to two shift clock periods selects short strobe mode. Pulse widths from 3 clock periods on wards select long strobe mode. The strobe signal does not need to be active throughout the transmission period since an internal bit counter generates the necessary timing for 8 or 16 bit periods depending on the selected output format for serial PCM transmission. Transmit PCM Data Output This Tristate output shifts out PCM data from the Codec's A/D converter and is activated during the transmission of serial data for 8 or 16 transmit clock periods following a rising edge on the transmit strobe signal. It is updated by the rising edges of the SCLK clock signal. The output goes back to high impedance after transmission of 8 or 16 data bits. 11 12 CS SCL DI DI 13 SDI DI 14 SDO DO 15 RXD DI 16 RXS DI 17 TXS DI 18 TXD DO REV. M Page 3 September 1998 AS3502 Pin Description (continued) Pin # 19 Name SCLK Type DI Function Serial PCM Shift Clock Input This pin acts as shift clock input signal for the externally provided signal for serial PCM data transfer. The frequency may vary from 128 kHz to 4.096 MHz in 8 kHz increments and should be synchronized to MCLK. In the receive direction the bitstream is latched with the falling edge of this clock. In the transmit direction the bitstream is shifted out with the rising edges of this clock. Master Clock Input This signal is the timing reference for all internal operations. The clock frequency must be a integer multiple of 2.048 MHz with a maximum of 18.432MHz and must be synchronized to SCLK. The required master clock dividing ratio is selected by setting the DIV3 -DIV0 bits in the Digital Control Register. Digital Negative Supply Voltage Input Differential Toneringer Outputs These digital outputs provide square or sine wave signal for driving transducers directly. TRO+ and TRO- are operating in push/pull mode providing peak to peak voltage swing of 2 x VDD.The output volume is programmable and is accomplished either through pulse density modulation or through pulse width modulation. Differential Earpiece Outputs These two pins are the outputs of the differential earpiece amplifier driving either dynamic earpieces with 150 impedance or ceramic transducers with up to 50nF directly. The signal reference on both pins is DC referenced to the internally generated Analogue Ground which is appr. 1/2 VDD. Analogue Negative Supply Voltage Input Differential Loudspeaker Outputs These two pins are the outputs of the differential loudspeaker amplifier that is capable driving dynamic speakers with 50 impedance directly. The maximum output power is 50mW. The signal reference on both pins is DC referenced to the internally generated Analogue Ground which is appr. 1/2 VDD. AO: Analogue Output DO: Digital Output SI: Supply Input 20 MCLK DI 21 22 23 GND TR+ TR- SI DO DO 24 25 EPEP+ AO AO 26 27 28 AVSS SP+ SP- SI AO AO AI: Analogue Input DI: Digital Input DI/O: Digital Input/Output REV. M Page 4 September 1998 AS3502 Functional Description Power-On Reset When power is applied first a power on reset signal is generated on chip which initializes AS3502: The on chip programmable AFE registers are set to their default values (those values are defined in the register allocation section), the tone control register is set to the default status and the serial interface is initialized. AS3502 remains in power down state until a software start-up command. An active Low signal with a duration of min. 25 s on the power on reset pin can be used to externally reset the device AS3502. For normal operation this pin must be pulled High. Power Up Mode AS3502 is powered up through a one byte start-up command. The byte written into the Digital Control Register DC allows to individually enable the transmit and the receive section. If the transmit channel is enabled first, the receive channel may be enabled any time without any restrictions. On enabling the receive channel and subsequent enabling of the transmit channel the PCM strobe signals TXS and RXS have to be tied together. The configuration information written into the AC and AG define which analogue transducer interfaces will be enabled on power up. The PCM output TXD remains in Tristate until the second frame synchronization signal after start-up. Any of the programmable registers may be modified while AS3502 is in active mode. Power Down Mode In power down mode all chip functions except the serial interface are kept inactive. All analogue functions are powered down and all digital outputs are put into Tristate mode. In this operating state the internal registers are normally configured to the desired values prior to the start-up command. The chip can be brought into power down mode any time through a power down command written into the DC Register. In this case all programmable registers retain their programmed values. Analogue Input interface The AS3502 input interface provides two identical differential inputs e.g. for a handset microphone and for a handsfree microphone. The input sources are selected through the AG register. Clipping of signals with arbitrary DC offset must be avoided by capacitive coupling. The input impedance of 2 x 30 k is compatible with both electret and dynamic microphones. Each input is connected through an analogue input multiplexer to a low noise high gain preamplifier. The gain is software programmable through register AG from +16 to +46 dB in 6 dB steps with a tolerance of 0.2 dB. This wide range REV. M guarantees optimum usage of the A/D converter dynamic range with various transducers. Analogue Output Interface The AS3502 output interface provides differential outputs for an earpiece, for a loudspeaker and for a toneringer. The output stages are selected through the AC register. The earpiece output driver is a fully differential amplifier that is capable of driving 3.2Vpp into a 150 transducer directly and is gain programmable in three steps from -12 dB to +6 dB through the AG register. The +6 dB step allows to drive ceramic earpiece transducers or to boost the receive amplitude. The loudspeaker driver is a fully differential power amplifier with a peak output power of 50 mW into a 50 loudspeaker. This output allows loudhearing and handsfree operation under software control. The tone ringer outputs are digital push/pull outputs with rail to rail voltage swing that capable of driving various toneringers. For volume control the output signal may be either pulse density modulated or pulse width modulated under software control. Transmit Section The scaled analogue input signal enters a 1st order RC antialiasing filter with a corner frequency of approx. 40 kHz. This filter eliminates the need for any off chip filtering as it provides sufficient attenuation at 1.024 MHz to avoid aliasing. From there the bandlimited signal is fed to a 2nd order Sigma Delta modulator with a sampling frequency of 1.024 MHz. A factory trimmed voltage reference guarantees accurate absolute transmit gain (0 dBm0 reference level). The modulator is followed by a digital decimation filter that transforms the resolution in time to resolution in amplitude. The decimation filter is followed by a minimum phase 5th order IIR filter implementing the CCITT lowpass portion of the encoder bandpass frequency characteristics. Finally a 3rd order IIR high pass filter implements the highpass portion of the encoder bandpass frequency characteristics according to CCITT specifications. The digitally filtered signal is further fed to a digital gain setting stage which allows to program the gain from -38 to +10 dB with a tolerance of better than 0.05 dB from 0 to +6 dB to compensate for transducer sensitivity variations. The same stage may additionally be used for digital volume control for transmit volume attenuation. This feature may be used for software based handsfree voice switching algorithms. In case of 16 bit linear mode the voice band signals are converted to a PCM two's complement 12 data bit plus sign bit format with a sample rate of 8 kHz and Page 5 September 1998 AS3502 shifted out of the encoder under control of an externally applied shift clock signal SCLK. In case of 8-bit companded mode the voice band signals are converted to a PCM two's complement 7 data bit plus sign bit A-Law format with a sample rate of 8 kHz and shifted out of the encoder under control of an externally applied shift clock signal SCLK. Receive Section In case of 16 bit linear mode PCM data is shifted into the input shift register at a clock rate determined by the shift clock SCLK every 128 s. 13 bits of PCM data are transferred to the receive latch that holds the data throughout the conversion process. In case of 8-bit companded mode PCM data is shifted into the input shift register at a clock rate determined by the shift clock SCLK every 128s and converted from A-Law format to 13-bit linear format. Optionally a programmable digital sidetone stage adds a certain amount of the transmit signal to the receive path for natural acoustic performance. The sidetone range can be adjusted from -48 dB to 0 dB with a default value of -18 dB. Both signals are combined and fed to a digital gain setting stage which allows to program the gain from -42 to +6 dB with a tolerance of 0.05 dB from 0 to -6dB to compensate for transducer sensitivity variations. The same stage may additionally be used for digital volume control for receive volume attenuation. This feature may be used for software based handsfree voice switching algorithms. The gainsetting stage is followed by a digital filter that bandlimits the signal according to CCITT recommendations and that converts the resolution in amplitude to resolution in time through interpolation. The output signal is fed to a digital 2nd order sigma delta modulator with a sampling rate of 1.024 MHz. The bit stream is further fed to a combined 1 bit DAC / 2nd order SC Lowpass filter with an corner frequency of 8 kHz and further to a 1st order RC active smoothing filter that provides additional filtering of out of band signals. The loudspeaker volume may be controlled digitally through the Receive Digital Gain Register DGR. Tone Generator AS3502 contains a powerful tone generator that is capable of generating all European country specific ring/ call progress tones and DTMF tones for audible feedback in the receive path or inband signalling tones in the transmit path under software control. The tone generator operation modes are programmable through 13 8-bit registers that are accessed through the serial control interface. (See register description for further details). Since all melody functions are handled by the AS3502 tone generator hardware only a minimum amount of software overhead for the controlling microprocessor is necessary. The tone generator consists of a single /dual tone synthesizer, a six tone sequencer, a cadence counter and a repetition counter. Frequency Generator For in band signalling a square wave or sine signal with precise DTMF capability is generated. The tones may be added to the receive section or injected into the transmit section. For tone ringing a square wave push/pull signal is generated on the TRO+ and TRO-. digital outputs. Transmit Tone Volume Control For sine wave forms the transmit PCM level is controlled by a 0 /-2.5 dB attenuation block and additionally by the digital transmit gain stage (DGX). For square wave forms the transmit PCM level is controlled by the V1 register and the DGX register. Receive Tone Volume Control The receive amplitude of sine wave signals may be controlled via the V2 register. The receive amplitude of square wave signals may be controlled by both the V1 and the V2 register. Tone Ringer Volume Control The output volume is programmable through the V1 register and is accomplished either through pulse density modulation or through pulse width modulation. For pulse density volume control the amplitude is controlled through the V1 register. Start Melody TRO+ TROPW = 0 T/2 T/2 Pulse Density Volume Control For pulse width volume control the R0 counter is used where it generates the duty cycle. In this case the repetition has to be controlled by the microprocessor through software. REV. M Page 6 September 1998 AS3502 Start Melody R0 < T/2 TRO+ TROPW = 1 CP: Cadence Period S1 S2 S3 S4 S5 S6 S1 S2 S3 R0 < T/2 CO: Cadence On Time Burst=1 T/2 T/2 Cadence Counter Pulse Width Volume Control Sequencer The sequencer controlling the synthesizer is a six step rotating shift register that is controlled by a cadence counter. Each location in the two sequence control registers (SC1, SC2) contains the value of one out of three different frequencies or the value of a tone pause that are played in consecutive order. In DTMF mode the 6-bit shift register is split up into two 3-byte shift registers. In this mode the cadence steps are interleaved as S1/S4, S2/S5, S3/S6 where the SC1 register defines the high group tones with an attenuation of 2.5 dB and where the SC2 register defines the low group tones. Repetition Counter The repetition counter controls either the duration (RO) and repetition (RP) of the melody sequence or the volume for pulse width volume control of the tone ringer output. In repetition mode the repetition counter may be operated in continuous mode where the ringing signal is turned on and off with the RP and R0 period or in single shot mode where the ringing signal is active for the R0 period. only. Each tone signalling sequence must be started with this counter: Repetition Period (RP) and Repetition On Time (RO) are programmed with an 8-bit value . RP: Repetition Period S1 S2 S3 S4 S5 S6 S1 S2 S3 S1 Single Tone: S6 S5 S4 S3 S2 S1 SC1 Dual Tone: S6 S5 S4 S3 SC2 S2 S1 MUX RO: Repetition On Time Repetition Counter . Tone Sequencer Cadence Generation The cadence counter determines the sequencer rotation speed and the on/ off timing characteristics of the tones and controls both the sequencer shift clock and the tone synthesizer on/ off time. The tone off time allows to insert pauses on switching from one frequency to the other. Cadence Period (CP) and Cadence On Time (CO) are programmed with an 8-bit value. The CS bit defines two time spans with different resolution: PCM Serial Interface The AS3502 5-wire PCM port interfaces directly to many serial port standards. The PCM data word is either formated in 16-bit linear format with 13 bit 2s complement data justified left where the last three LSB bits are reserved or formatted according to 8-bit A-Law format with alternate mark inversion (AMI) meaning that the even bits are inverted per CCITT G711 specification. REV. M Page 7 September 1998 AS3502 PCM Level 8-Bit A-Law Format 16-Bit Linear Format DDDDDDDDDDDDDDDDDDDDDDDD 765432101111119876543210 VIN = VIN = VIN = VIN = + Full Scale +0-Code -0-Code - Full Scale 1 1 0 0 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 5 0 0 1 1 4 1 0 1 0 3 1 0 1 0 2 1 0 1 0 1 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 x x x x x x x x x x x x x: not used The interface supports short and long strobe synchronisation modes and full duplex synchronous operations of both receive and transmit section. PCM data is written into the transmit register and shifted out in 8 or 16 clock cycles by the transmit shift register. In the receive direction serial input 8 or 16 samples are converted into parallel format by the receive shift register and hereafter buffered in the receive latch. This double buffered hardware I/O scheme guarantees minimum port latency and increased channel service time. Both shift registers have separate strobe signals for asynchronous time slot operation of transmit and receive channel and are clocked by a common shift clock signal that may vary from 64 kHz up to 4.096 MHz and that must be locked to the master clock. The strobe signals have to be synchronised to the shift clock and should have a repetition rate of 8 kHz. 50 ppm. Short Strobe Mode This is the default mode on powering up the device. The transmit and receive strobe inputs must be one bit shift clock long and have to be High during a falling edge of the respective bit shift clocks (see PCM Timing Diagramme) In the transmit section the next rising edges of SCLK enable the TXD output buffer and shift out PCM data bits. The falling edge of the last bit shift clock SCLK disables the TXD output buffer. In the receive section the next falling edge of SCLK shifts in PCM data bits at RXD. Long Strobe Mode The serial port enters the long strobe mode if both strobe pulses (TXS, RXS) are more than three bit clock periods long (See PCM Timing Diagramme). In the transmit section the next rising edge of SCLK or TXS, whichever comes later, clocks out the first bit. The effect of the transmit strobe occurring after the shift clock is to shorten the first bit at the TXD output. The following rising edges of the SCLK shift out the remaining data bits. The TXD output is disabled by the last falling SCLK edge or by the TXS signal going Low, whichever comes later. In the receive section a rising edge on the receive strobe input RXS will initiate the PCM data on RXD pin to be shifted into the receive shift register with the falling edges of SCLK. REV. M Serial Control Interface The internal operation of AS3502 is controlled by a 4wire serial port that is designed to write and read back control and status information from any serial microprocessor port. It consists of a 16 bit shift register with 8 address bits and 8 data bits. The first byte is the Address Byte that is clocked in serially by asserting the CS line for 8 clock cycles. The MSB address bit in the address field defines whether the data transfer is a write or a read operation. The second byte is the Command Data Byte that is clocked in by keeping CS Low for another 8 clock cycles. The address decoder latches the address bits received into a register after 8 clock cycles. It operates fully autonomously and constantly cycles through 3 states: * Load address decoder * Calculate address and type of data transfer * Data transfer After decoding the data byte is latched into the decoded register during a write operation or retrieved from the selected register during a read operation. Data is retrieved by asserting the CS line and by shifting 8 address bits into the input shift register through SDI. The next 8 clock cycles shift out the data byte through SDO. The full shift register is shifted out where the 8 MSB bits are shifted out as Hi-Z. Data states on the SDO line can only change with the falling edge of SCL. Data on the SDI line is shifted in with the rising edge of SCL. All commands are preceded by the start condition, which is a High to Low transition of the CS line. The AS3502 continuously monitors this line for the start condition and does not respond to any command until this condition has been met. CS may either be kept Low for 16 clock cycles or may go High after 8 clock cycles and go Low again for the next 8 clock cycles when programming different register locations. All communications are terminated by a stop condition, which is a Low to High transition of CS after 16 shift clock cycles. The stop condition is also used to place the AS3502 serial control interface in the standby power mode. Page 8 September 1998 AS3502 CS SCL SERIAL WRITE SDI R/W =0 X X A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 ADDRESS BYTE SERIAL READ SDI R/W =1 X X A4 A3 A2 A1 A0 X X X DATA BYTE X X X X X ADDRESS BYTE Z Z Z Z Z Z Z Z D7 D6 D5 D4 D3 D2 D1 D0 SDO DATA BYTE Serial Control Interface Address bit A4 selects between the upper and the Programmable Functions lower register bank. Address bit A7 defines whether 19 8-bit internal registers are provided for control and the operation will be a write or read operation. operation status monitoring. The addresses are divided into two register banks with 16 locations each. REV. M Page 9 September 1998 AS3502 Register Bit Summary REGISTER ADDR A4- A0 Digital Control Analogue Control Analogue Gain TX Digital Gain Sidetone Gain RX Digital Gain Tone Control DC AC AG DGX SG DGR TC 00h 01h 02h 03h 05h 07h 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch D7 A / LIN 0 0 DGX7 SG7 DGR7 TRINJ 0 0 F17 0 F27 0 F37 0 RP7 RO7 CP7 CO7 D6 ENRX 0 ENM2 DGX6 SG6 DGR6 RXINJ 0 0 F16 V14 F26 0 F36 0 RP6 RO6 CP6 CO6 D5 ENTX LOOP ENM1 DGX5 SG5 DGR5 TXINJ S31 S61 F15 V13 F25 V23 F35 0 RP5 RO5 CP5 CO5 DATA BIT NUMBER D4 DIV3 CLRX AGX2 DGX4 SG4 DGR4 CS S30 S60 F14 V12 F24 V22 F34 0 RP4 RO4 CP4 CO4 D3 DIV2 CLTX AGX1 DGX3 SG3 DGR3 D2 DIV1 ENEP AGX0 DGX2 SG2 DGR2 D1 DIV0 ENSPK AGR1 DGX1 SG1 DGR1 TONE MODE S11 S41 F11 F19 F21 F29 F31 F39 RP1 RO1 CP1 CO1 D0 0 NOV AGR0 DGX0 SG0 DGR0 START S10 S40 F10 F18 F20 F28 F30 F38 RP0 RO0 CP0 CO0 BURST SHAPE MODE S21 S51 F13 V11 F23 V21 F33 PS RP3 RO3 CP3 CO3 S20 S50 F12 V10 F22 V20 F32 PW RP2 RO2 CP2 CO2 Sequence Control 1 SC1 Sequence Control 2 SC2 Frequency Control 1 Volume Control 1 Frequency Control 2 Volume Control 2 Frequency Control 3 Volume Control 3 Repetition Period Repetition On Time Cadence Period Cadence On Time F1 V1 F2 V2 F3 V3 RP RO CP CO REV. M Page 10 September 1998 AS3502 1) DIGITAL CONTROL REGISTER This register controls the master clock divider, the enabling of the transmit channel, the enabling of thereceive channel and the PCM format. DC Name Default D7 A/LIN 0 D6 ENRX 0 D5 ENTX 0 D4 DIV3 0 D3 DIV2 0 D2 DIV1 0 D1 DIV0 0 D0 X X Bit No D7 D6 Symbol A/LIN Name and Description D5 D4- D1 A-Law / Linear Select. In default mode or when set to Low 16-bit linear PCM format is selected. When set to High 8-bit A-Law PCM format is selected. Enable Receive Channel. When set to High the Receive Channel including the selected ENRX output driver, the master clock divider and the Receive PCM interface are enabled. When set to Low the Receive Channel will be powered down. Enable Transmit Channel. When set to High the Transmit Channel including the seENTX lected microphone input, the master clock divider and the Transmit PCM interface are enabled. When set to Low the Transmit Channel will be powered down. DIV3-DIV0 Master Clock Prescaler Setting Bits. Master Clock Frequency DIV3 DIV2 DIV1 DIV0 State 0 0 0 0 /1 2.048 MHz 0 0 0 1 /2 4.096 MHz 0 0 1 0 /3 6.144 MHz 0 0 1 1 /4 8.192 MHz 0 1 0 0 /5 10.240 MHz 0 1 0 1 /6 12.288 MHz 0 1 1 0 /7 14.336 MHz 0 1 1 1 /8 16.386 MHz 1 0 0 0 /9 18.432 MHz 2) ANALOGUE CONTROL REGISTER The Analogue Control Register enables the output drivers and the muting of the receive voice channel. Further it allows to monitor clipping in both the transmit and the receive channel for software based automatic gain control. AC Name Default D7 0 0 D6 0 0 D5 LOOP 0 D4 CLIPRX 0 D3 CLIPTX 0 D2 ENEP 0 D1 ENSPK 0 D0 NOV 0 REV. M Page 11 September 1998 AS3502 Bit No D7-D6 D5 D4 D3 D2 D1 Symbol LOOP CLIPRX CLIPTX ENEP ENSPK Name and Description These bits are Low during a read operation. Loop Back Mode Enable. When set to High a loop back mode is enabled where the output of the sigma delta converter is directly fed to the input of the 1-bit DAC and where the output of the interpolation filter is fed to the input of the decimation filter. Receive Channel Clipping. On reading this bit a High indicates an overload condition in the receive channel. Transmit Channel Clipping. On reading this bit a High indicates an overload condition in the transmit channel. Enable Earpiece. When set to High the earpiece driver is enabled. When set to Low the earpiece driver is powered down. Enable Speaker. When set to High the loudspeaker driver is enabled. When set to Low the loudspeaker driver is powered down. Both drivers may be activated if necessary e.g. for call progress monitoring. No Voice. When set to High the voice signal in the receive channel is muted. D0 NOV 3) ANALOGUE GAIN REGISTER This register contains control bits for enabling on of the two microphone inputs and data for setting the analogue microphone amplifier and earpiece amplifier gains. AG Name Default D7 0 0 D6 ENM2 0 D5 ENM1 0 D4 AGX2 0 D3 AGX1 1 D2 AGX0 0 D1 AGR1 0 D0 AGR2 0 Bit No D6 D5 D4-D2 Symbol ENM2 ENM1 AGX2 AGX0 Name and Description Enable Microphone 2 Input. When set to High the microphone amplifier is connected to the MIC2 + and MIC2 - inputs. Enable Microphone 1 Input. When set to High the microphone amplifier is connected to the MIC1+ and MIC1- inputs. Analogue Transmit Gain Setting (AGX). AGX0 Microphone Gain AGX2 AGX1 0 0 0 +15.5 dB 0 0 1 +21.5 dB 0 1 0 +27.5 dB Default Value 0 1 1 +33.5 dB 1 0 0 +39.5 dB 1 0 1 +45.5 dB Analogue Receive Gain Setting. (AGR). Earpiece Gain AGR1 AGR0 0 0 -12 dB Default Value 0 1 -6 dB 1 0 0 dB 1 1 +6 dB D1- D0 AGR1 AGR0 REV. M Page 12 September 1998 AS3502 4) TRANSMIT DIGITAL GAIN REGISTER This register contains the 8 bit coefficient for digital transmit gain setting. DGX Name Default D7 DGX7 0 D6 DGX6 1 D5 DGX5 1 D4 DGX4 0 D3 DGX3 1 D2 DGX2 1 D1 DGX1 0 D0 DGX0 1 Bit No D7-D0 Symbol DGX7DGX0 Name and Description Transmit Digital Gain Setting (DGX). An 8-bit coefficient written into this register allows to trim the gain from -38 dB to +10 dB. The coefficient in decimal format for a given gain is calculated as: DGX ( ) X = 77 x 10 20 Coefficient 154 137 123 109 97 87 77 55 39 Coefficient Transmit Gain +6 dB 27 +5 dB 19 +4 dB 13 +3 dB (Default Value) 10 +2 dB 7 +1 dB 5 0 dB 3 - 3 dB 2 - 6 dB 1 Transmit Gain -9 dB -12 dB -15 dB -18 dB -21 dB -24 dB -28 dB -32 dB -38 dB 5) SIDETONE GAIN REGISTER This register contains an 8 bit coeficient for a digital sidetone. The sidetone may be disabled by writing 00h into this register. SG Name Default D7 SG7 0 D6 SG6 0 D5 SG5 1 D4 SG4 0 D3 SG3 0 D2 SG2 0 D1 SG1 0 D0 SG0 0 Bit No D7-D0 Symbol SG7-SG0 Name and Description Digital Sidetone Attenuation Control. An 8-bit coefficient written into this register allows to control the sidetone attenuation in the receive channel. The sidetone attenuation range is 0 dB to -48dB. The coefficient in decimal format for a given attenuaton is ( SG ) X = 256 x 10 20 The sidetone default coefficient is 32 which corresponds to an attenuation of -18 dB. calculated as: REV. M Page 13 September 1998 AS3502 6) RECEIVE DIGITAL GAIN REGISTER This register contains an 8-bit coefficient for digital receive gain setting. DGR Name Default D7 DGR7 0 D6 DGR6 1 D5 DGR5 0 D4 DGR4 1 D3 DGR3 1 D2 DGR2 0 D1 DGR1 1 D0 DGR0 1 Bit No D7-D0 Symbol DGR7DGR0 Name and Description Receive Digital Gain Setting (DGR). An 8-bit coefficient written into this register allows to fine trim the receive path gain from -42 to +6 dB. The coefficient in decimal format for a given gain is calculated as: ( DGR ) X = 127.7 x 10 20 Coefficient 128 114 101 90 81 72 64 46 32 Coefficient Receive Gain 0 dB 23 -1 dB 16 -2 dB 11 -3 dB (Default Value) 8 -4 dB 5 -5 dB 4 -6 dB 3 -9 dB 2 -12 dB 1 Receive Gain -15 dB -18 dB -21 dB -24 dB -27 dB -30 dB -33 dB -36 dB -42 dB 7) TONE CONTROL REGISTER This register controls the various tone generator operation modes and the tone desstinations. TC Name Default D7 TRINJ 0 D6 RXINJ 0 D5 TXINJ 0 D4 CS 0 D3 BURST MODE 0 D2 SHAPE 0 D1 TONE MODE 0 D0 START 0 REV. M Page 14 September 1998 AS3502 Bit No D7 Symbol TRINJ Name and Description Tone Ringer Inject. When set to High the tone generator is connected to the toneringer output. When set to Low the TRO+ and TRO- outputs are forced to high impedance state. Receive Inject. When set to High the tone generator is connected to the AS3502 receive section. Transmit Inject. When set to High the tone generator is connected to the AS3502 transmit section. Cadence Slow Bit. When set to High the cadence step size resolution is 4 ms. When set to Low the cadence step size resolution is 1 ms. When set to High tone burst mode operation is selected. When set to High square wave mode is selected. When set to Low sine wave mode is selected Tone Mode Bit. When set to High dual tone mode is selected. When set to Low single tone mode is selected. Start Melody. When set to High the tone generation is enabled. This bit acts as single byte on/off sequence. D6 D5 D4 D3 D2 D1 D0 RXINJ TXINJ CS BURST MODE SHAPE TONE MODE START 8) SEQUENCE CONTROL REGISTER 1 This register contains the frequency codes for the first three steps of the six tone cadence. SC1 Name Default D7 0 0 D6 0 0 D5 S31 x D4 S30 x D3 S21 x D2 S20 x D1 S11 x D0 S10 x Bit No D7, D6 D5, D4 Symbol S31, S30 Name and Description Not used; will be low during read Cadence Step 3: 00: No Tone 01: Frequency/Volume Register 1 is selected 10: Frequency/Volume Register 2 is selected 11: Frequency/Volume Register 3 is selected Cadence Step 2 00: No Tone 01: Frequency/Volume Register 1 is selected 10: Frequency/Volume Register 2 is selected 11: Frequency/Volume Register 3 is selected Cadence Step1 00: No Tone 01: Frequency/Volume Register 1 is selected 10: Frequency/Volume Register 2 is selected 11: Frequency/Volume Register 3 is selected S21, S20 D1, D0 S11, S10 REV. M Page 15 September 1998 AS3502 9) SEQUENCE CONTROL REGISTER 2 This register contains the frequency codes for the second three steps of the six tone cadence. SC2 Name Default D7 0 0 D6 0 0 D5 S61 X D4 S60 X D3 S51 X D2 S50 X D1 S41 X D0 S40 X Bit No D7, D6 D5, D4 Symbol S61,S60 Name and Description Not used; will be low during read Cadence Step 6: 00: No Tone 01: Frequency/Volume Register 1 is selected 10: Frequency/Volume Register 2 is selected 11: Frequency/Volume Register 3 is selected Cadence Step 5 00: No Tone 01: Frequency/Volume Register 1 is selected 10: Frequency/Volume Register 2 is selected 11: Frequency/Volume Register 3 is selected Cadence Step 4 00: No Tone 01: Frequency/Volume Register 1 is selected 10: Frequency/Volume Register 2 is selected 11: Frequency/Volume Register 3 is selected D3, D2 S51, S50 D1, D0 S41, S40 10) FREQUENCY CONTROL REGISTER 1 This register contains eight bits of the 10-bit coefficient of the first frequency. F1 Name Default D7 F17 X D6 F16 X D5 F15 X D4 F14 X D3 F13 X D2 F12 X D1 F11 X D0 F10 X Bit No D7-D0 Symbol F17-F10 Name and Description A 10-bit coefficient (X) written into this register and into bits D0 and D1 of V1 allows to programme the first frequency from 3.9 Hz to 3996 Hz. The coefficient for a given frequency can be calculated as: f (Hz )* 256 ; X = ( 1...1023) X= 1000 11) VOLUME CONTROL REGISTER 1 This register contains the remaining two bits of the first frequency coefficient and volume control data for pulse density volume control of square waves. REV. M Page 16 September 1998 AS3502 V1 Name Default D7 0 X D6 V14 X D5 V13 X D4 V12 X D3 V11 X D2 V10 X D1 F19 X D0 F18 X Bit No D6-D2 Symbol V14-V10 Name and Description A 5 bit coefficient (X) written into this register allows to programme both the tone ringer attenuation in pulse density mode and the attenuation of the tone generator in square wave mode. The coefficient in decimal format for a given attenuation can be calculated as: Volume(dB ) ) ;X= ( 1...31) X = 31* 10^ ( 20 V1 VOUT = 2 *VDD *10^( ) (V) 20 In tone generator square wave mode a 4-bit coefficient using bits V13 to V10 allows to programme the volume where coefficient in decimal format for a given volume can be calculated as: Volume(dB ) ) ;X= (0...15) X = 16 * 10^ ( 20 In receive direction the absolute output value on the speaker and earpiece outputs depends on AGR and V2. VOUTEP= 6.14 dBm + V2C + V1 + AGR (dBm) VOUTSP=6.14 dBm + V2 + V1 + 3 dB (dBm) In transmit direction the output value depends on V1 and DGX. F19-F18 VOUT = 6.14 dBm0 + V1 + DGX (dBm0) These bits are the two most significant bits of the 10-bit frequency coefficient. 12) FREQUENCY CONTROL REGISTER 2 This register contains eight bits of the 10-bit coefficient of the second frequency. F2 Name Default D7 F27 X D6 F26 X D5 F25 X D4 F24 X D3 F23 X D2 F22 X D1 F21 X D0 F20 X Bit No D7-D0 Symbol F27-F20 Name and Description A 10-bit coefficient (X) written into this register and into bits D0 and D1 of V2 allows to programme the second frequency from 3.9 Hz to 3996 Hz. The coefficient in decimal format for a given frequency can be calculated as: f (Hz )* 256 X= 1000 REV. M Page 17 September 1998 AS3502 13) VOLUME CONTROL REGISTER 2 This register contains the remaining two bits of the second frequency coefficient, and coarse and fine tone volume control data for the receive direction. V2 Name Default D7 0 X D6 0 X D5 V23 X D4 V22 X D3 V21 X D2 V20 X D1 F29 X D0 F28 X Bit No D5-D3 Symbol V23-V21 Name and Description Receive Tone Coarse Volume Control ( V2C) V21 Attenuation V23 V22 0 0 0 - 10 dB 0 0 1 - 16 dB 0 1 0 - 22 dB 0 1 1 - 28 dB 1 0 0 - 34 dB 1 0 1 - 40 dB Sine Tone Fine Volume Control (V2F) V20 Attenuation 0 0 dB 1 - 2.5 dB In transmit direction the sineoutput value depends on V2F and DGX: VOUTSINE = 3.8 dBm + V2F + DGX (dBm0) VOUTDTMF ROW TONE = -2.2dBm + DGX (dBm0) VOUTDTMFCOLUMN TONE = -4.7dBm + DGX (dBm0) In receive direction the sine output value on earpiece and speaker depends on V2C, V1 and AGR: VOUTEP= 3.8 dBm + V2C + V2F+ AGR (dBm) VOUTSP= 3.8 dBm + V2C + V2F+ 3dB (dBm) These bits are the two most significant bits of the 10-bit frequency coefficient. D2 V20 D1-D0 F29-F28 REV. M Page 18 September 1998 AS3502 14) FREQUENCY CONTROL REGISTER 3 This register contains eight bits of the 10-bit coefficient of the third frequency. F3 Name Default D7 F37 X D6 F36 X D5 F35 X D4 F34 X D3 F33 X D2 F32 X D1 F31 X D0 F30 X Bit No D7-D0 Symbol F37-F30 Name and Description A 10-bit coefficient (X) written into this register and into bits D0 and D1 of V3 allows to programme the third frequency from 3.9 Hz to 3996 Hz. The coefficient in decimal format for a given frequency can be calculated as: f (Hz )* 256 ; X = (1...1023) X= 1000 15) VOLUME CONTROL REGISTER 3 This register contains two bits of the third frequency coefficient and tone ringer volume mode control bits. V3 Name Default D7 0 X D6 0 X D5 0 X D4 0 X D3 PS X D2 PW X D1 F39 X D0 F38 X Bit No D3 D2 D1-D0 Symbol PS PW F29-F28 Name and Description Pulse Width Slow Bit. When set to High the pulse width step size is 4 s. When set to Low the pulse width step size is 1 s. Tone Ringer Volume Control Mode Bit. When set to Low pulse density volume control is selected. When set to High pulse width volume control is selected. These bits are the two most significant bits of the 10-bit frequency coefficient. 16) REPETITION PERIOD REGISTER RP Name Default D7 RP7 X D6 RP6 X D5 RP5 X D4 RP4 X D3 RP3 X D2 RP2 X D1 RP1 X D0 RP0 X Bit No D7-D0 Symbol RP7-RP0 Name and Description An 8-bit value written into this register allows to set the repetition period with 32ms accuracy. Time(ms) X= - 1; X= (1...255) 32ms REV. M Page 19 September 1998 AS3502 17) REPETITION ON REGISTER RO Name Default D7 RO7 X D6 RO6 X D5 RO5 X D4 RO4 X D3 RO3 X D2 RO2 X D1 RO1 X D0 RO0 X Bit No D7-D0 Symbol RO7-RO0 Name and Description An 8-bit value written into this register allows to set the repetition on time with 32ms accuracy. If this time exceeds the repetition period time, continuous operation will be performed. Repetition times can only be generated when using pulse density volume control mode. Time(ms) ; X= (1...255) 32ms If pulse width volume control mode is selected, an 8-bit value written into this register allows to set the duty cycle of the tone ringer outputs with two different accuracies depending on the PS bit in the volume Control Register 3 : Time(s) ; X= (1...255) PS=0: X = 1s Time(s) ; X= (1...255) PS=1: X = 4s X= 18) CADENCE PERIOD REGISTER CP Name Default D7 CP7 X D6 CP6 X D5 CP5 X D4 CP4 X D3 CP3 X D2 CP2 X D1 CP1 X D0 CP0 X Bit No D7-D0 Symbol CP7-CP0 Name and Description A n 8-bit value written into this register allows to set the cadence period with two different accuracies. If the SLOW bit in the TC register is set to Low the resolution is 1ms: Time(ms) X= - 1; X= (1...255). 1 (ms) If the SLOW bit in the TC register is set to High the resolution is 4ms: Time(ms) X= - 1; X= (1...255). 4(ms) REV. M Page 20 September 1998 AS3502 19) CADENCE ON REGISTER CO Name Default D7 CO7 X D6 CO6 X D5 CO5 X D4 CO4 X D3 CO3 X D2 CO2 X D1 CO1 X D0 CO0 X Bit No D7-D0 Symbol CO7-CO0 Name and Description An 8-bit value written into this register allows to set the cadence on time with two different accuracies. If the SLOW bit in the TC register is set to Low the resolution is 1ms: Time(ms) X= ; X= (1...255). 1 (ms) If the SLOW bit in the TC register is set to High the resolution is 4ms: Time(ms) X= ; X= (1...255). 4(ms) REV. M Page 21 September 1998 AS3502 Absolute Maximum Ratings* Supply Voltage................................................................................................................................-0.3VDD7 V Voltage applied on Any Input ........................................................................................... -0.3 VVINVDD+0.3 V Voltage applied on Digital Outputs................................................................................ -0.3 VVOUTVDD+0.3 V Input Current (all pins).................................................................................................................... IIN 50 mA Output Current .............................................................................................................................. IOUT 10 mA Storage Temperature Range........................................................................................................... -65 to +150C *Exceeding these figures may cause permanent damage. Functional operation under these conditions is not permitted Recommended Operating Conditions Symbol VDD TAMB VIN VOUT CLOCK SYNC Parameter Supply Voltage Operating Temperature Range Input Voltage Tristate Output Voltage Clock Frequency Synchronization Frequency Conditions Min. 3.0 -40 GND GND Typ.* 4.5 +25 Max. 5.5 +70 VDD VDD Units V C V V MHz kHz 2.048 8 * Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing DC Characteristics (-40C VIL VIH VOL VOH IL IOZ IDD IDD0 Parameter Input Low Level Input High Level Output Low Level Output High Level Input Leakage Current High Impedance Current Supply Current Power Down Current Conditions All digital inputs All digital pins 1.6 mA 1.6 mA VIN= GND to VDD VOUT= GND to VDD Outputs unloaded; VDD = 3 V TA= 25C VDD= 3.0 V Min. 0.7xVDD 2.4 Typ.* Max. Units 0.3xVDD V V 0.4 V V 10 10 10 5 A A mA A Analogue Interface With Microphone Input 1 & 2 (-40C Parameter Peak Input Level Nominal Input Level Transmit Gain Analogue Gain Range Analogue Gain Step Size Input Impedance Conditions Note 1; THD Min. Typ.* Max. 176 5.58 Units mVrms mVrms mVrms dB dB dB k MIC+ to MIC-,0.3 f 3.4kHz +16 +15.5 5.8 2 x 30 21.8 +31 +33.5 6.0 +52 +45.5 6.2 * Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing REV. M Page 22 September 1998 AS3502 Note 1: This corresponds to a +3.14 dBm0 signal at the PCM output which is equal to a PCM overload level of 4096; Analogue Interface with Earpiece Output (-40C Parameter Peak Overload Level Conditions Note 1 RL=150 THD= 2% GR=0 dB CL=60nF THD = 5% GR=+5 dB 0 dBm0 PCM Code GR=-15 dB EP + to EPGR = AGR + DGR Min. Typ.* Max. 1.12 2.8 Units Vrms Vp mVrms dB dB dB mV AOUT RL GREP AGREP VOFF Nominal Output Level Load Resistance Earpiece GainRange Analogue Gain Range Analogue Gain Step Size Output Offset Voltage 137.7 150 -18 -12 5.8 -15 6.0 100 +6 +6 6.2 * Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing Note 1: This corresponds to a +3.14dBm0 code at the PCM input which is equal to a PCM overload level of 4096; Analogue Interface with Speaker Output (-40C Parameter Peak Overload Level Load Resistance Speaker Receive Gain Range Speaker Analogue Gain Output Offset Voltage Conditions Note 1 RL=50 THD= 5%, GRSPK= + 3dB SPK+ to SPK GRSPK = AGRSPK + DGR SPK+ to SPK- Min. 1570 50 -3 Typ.* Max. Units mVrms dB dB mV 0 +3 100 +3 * Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing Note 1: This corresponds to a +3.14dBm0 code at the PCM input which is equal to a PCM overload level of 4096; Analogue Interface with Tone Ringer Output (-40C Parameter Max. Output Voltage Swing Load Capacitance Output Rise Time Output Fall Time Conditions TRO+ to TROTRO+ to TRO- Min. Typ.* 2 x VDD Max. 50 Units Vpp nF s s 100 CL = 50nF 100 CL = 50nF * Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing Note 1: See text for volume control Microphone Reference Voltage Output (-40C Parameter Reference Voltage Power Supply RejectionRatio Output Noise Conditions IL = 1 mA; Note 1 300 Hz to 3 kHz, 100 mVrms Note 2 300 Hz to 3.4kHz, Note 2 Min. 2.0 55 Typ.* 2.2 Max. 2.4 100 Units V dB V * Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing Note 1: VREF is turned off in power down mode Note 2: VREF must be filtered by a suitable RC lowpass filter. A typical setup is using a 500 microphone feeding resistor and a 22 F capacitor to ground. REV. M Page 23 September 1998 AS3502 Transmit Transmission Characteristics (-40C Symbol GXA GXAT GXAV GXAG DGX GTX Parameter Absolute Transmit Gain Trimming and Step Deviations Gain Variation with Temp. Gain Variation with Supply Gain Variation with Digital Gain Digital Gain Setting Range Gain Variation with Input Level Conditions 25 C, Note 1, MIC1 Input Steps: 16dB, 22dB, 28dB, 34dB, 40dB Min. Typ.* Max. 0.3 Units dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB s 0.1 0 dB DGX +6 dB See text for coefficient calculation 1020 Hz tone ; AGX=40 dB; DGX=0 dB -40 to +3 dBm0 -50 to -40 dBm0 -50 to -55 dBm0 Relative. to gain at 1020 Hz @ -10dBm0 50 Hz 60 Hz 100 Hz 200 Hz 300 to 3000 Hz 3400 Hz 3400 Hz to 4000 Hz 4000 Hz to 4600 Hz 4.6 kHz at--10 dBm0 8 kHz at -10 dBm0 0 dBm0 at 1500 Hz Relative to minimum 500 Hz 630 Hz 800 Hz 1000 Hz 1250 Hz 1600 Hz 2100 Hz 2500 Hz f = 1020 Hz , AGX=40 dB; DGX=0 dB; Note 4 0dBm0 -10dBm0 -30dBm0 -40dBm0 -45 dBm0 Inputs shorted; AGX=40 dB; DGX=0 dB 0.3 -3.4 kHz 10 Hz bandwidth; AGX=40 dB; DGX=0 dB VDD + 100 mVrms 0 to 50 kHz inputs shorted; measured on TXD 0.05 0.05 +6 0.2 0.4 0.8 -30 -30 -22 -0.1 0.2 0 Note 2 Note 3 0 GXAF Transmit Frequency Response -1.8 -0.2 -1.1 35 45 600 190 100 50 20 0 0 10 50 50 50 40 31 26 DIS PDX DDX Discrimination against Out -of Band Input Signals Absolute Group Delay Group Delay Distortion s s s s s s s s STDX Signal to Distortion Ratio ICNX SFNX PSRRX CT RX->TX Idle Channel Noise Single Frequency. Noise Transmit Power Supply Rejection Ratio Receive to Transmit Crosstalk -70 -75 50 75 dBp dBp dBp dBp dBp dBm0p dBm0 dBp dB * Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing Note 1: The tolerance of the absolute input level is defined by the trimming accuracy of the converter reference. (4000 - f ) (4000 - f ) 15 Note 2: GXAF = 15 sin - 1 Note 3: GXAF = 20 sin - 20 1200 1200 Note 4: Total distortion includes quantization and harmonic distortion; REV. M Page 24 September 1998 AS3502 Receive Transmission Characteristics (-40C Symbol GRA GRAT GRAV GRAG DGR GTR Parameter Absolute Receive Gain Trimming and Step Deviations Gain Variation with Temp. Gain Variation with Supply Gain Variation with Digital Gain Digital Gain Setting Range Gain Variation with Input Level Conditions 25 C, Note 1 Steps: 0dB, -6dB, -12dB Min. Typ.* Max. 0.3 Units dB dB dB dB dB dB dB dB dB dB dB dB dBm0 dBm0 s 0.1 0.05 0.05 0 0.2 0.4 0.8 -0.2 -0.25 -0.8 0.2 0.2 0 Note 2 -40 -50 370 0 0 0 10 20 30 60 110 50 50 36 31 26 -75 -78 50 50 75 GRAF SOS PDR DDR STDR ICNR SFNR PSRRR CT TX->RX -6 dB DGR 0 dB See text for coefficient calculation 1020 Hz tone -40 to +3 dBm0 -50 to -40 dBm0 -50 to -55 dBm0 Receive Frequency Response Relative to gain @ 1020 Hz, -10dBm0 0 Hz to 2400 Hz 2400 Hz to 3000 Hz 3400 Hz 3400 Hz to 4000 Hz Spurious Out-of Band Signals at 4.6 kHz @0 dBm0; 300 Hz f 3.4 kHz the Output 8k Hz @-0 dBm0; 300 Hz f 3.4 kHz Absolute Group Delay 0 dBm0 @ 800Hz Group Delay Distortion Relative to minimum 500 Hz 630 Hz 800 Hz 1000 Hz 1250 Hz 1600 Hz 2100 Hz 2500 Hz Signal to Distortion Ratio f = 1020 Hz , Note 3 0 dBm0 -10 dBm0 -30 dBm0 -40 dBm0 - 45 dBm0 Idle Channel Noise PCM +0 Code; AGR = + 6 dB Sampling Frequency. Noise selectively measured @ 8 kHz; AGR=+6 dB Receive VDD + 100 mVrms; PCM +0 Code Power Supply Rejection Ratio 0 - 4 kHz 4 - 50 kHz Transmit to Receive Crosstalk GR = -12 dB (4000 - f ) - 1 1200 -6 s s s s s s s s dBp dBp dBp dBp dBp dBm0p dBm0 dBp dB dB * Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing Note 1: The tolerance of the absolute level is defined by the trimming accuracy of the converter reference. Note 2: Note 3: GRAF = 13sin Total distortion includes quantization and harmonic distortion. REV. M Page 25 September 1998 AS3502 Tone Generator Characteristics (-40C -30 * Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing Note 1: In the transmit direction the sine tone level is controlled by the DGX register and the V2F bit. Note 2: In the transmit direction the DTMF level is controlled by the DGX register only. Note 3: In the transmit direction the square tone level is controlled by the V1 register and the DGX register. Levels exceeding 3.14 dBm0 are limited by the transmit saturation logic to 3.14 dBm0. Note 4: In the receive direction the sine tone level is controlled by the V2 and the AGR register. Note 5: In the receive direction the square tone level is controlled by the V1, V2C and the AGR register. Timing SpecificationsPCM Interface Timing (-40C REV. M Page 26 September 1998 AS3502 # 9 10 11 12 13 14 Parameter Hold Time from SCLK Low to Short Strobe Low Hold Time from SCLK Low to Long Strobe High Set Up Time from Long Strobe High to SCLK Low Hold Time from 3rd Period of SCLK Low to Strobe Low Delay Time from SCLK High to TXD Valid Delay Time to Valid Data from TXS or SCLK whichever comes later Delay Time from SCLK or TXS Low to TXD Disabled Set Up Time from RXD Valid to SCLK Low Hold Time from SCLK Low to RXD invalid Strobe Pulse Frequency Symbol tHCSSL tHCLSH tSLSCL tHCLSL tDCD tDSD tDCZ tSDC tHCD fSTB Condition Min 30 0 30 30 Typ Max Units ns ns ns ns CL= 100 pF + 2 TTL Loads CL= 100 pF + 2 TTL Loads 80 80 ns ns 15 16 17 18 80 30 20 8 ns ns ns KHz * Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing Note 1: A 50:50 duty cycle must be used for 2.048MHz operation Note 2: AS3502 provides a software programmable input clock divider that is programmable from 1:1 to 1:9 1 MCLK 5 6 4 SCLK 7 2 3 8 9 1 2 3 4 16 (8) TXS, RXS (SHORT) 10 11 12 TXS, RXS (LONG) 13 14 15 TXD 16 17 MSB D D D D LSB RXD MSB D D PCM Timing Diagramme REV. M Page 27 September 1998 AS3502 Serial Control Interface Timing (-40C Symbol fSCLK tWCH tWCL tFC tRC tHCS tHSC tSSC tSSC0 tSDC tHCD tDCD tDSD tDDZ Condition Min. 128 160 160 Typ.* Max. 2048 Units kHz ns ns ns ns ns ns ns ns ns ns 50 50 For 1st SCL For 8th SCL 10 100 60 SDO is not enabled for a single byte transfer 60 50 50 100pF + 2 LSTTL Loads Only valid for dual chip selects 15 80 80 80 ns ns ns 5 SCL 6 1 3 8 4 2 8 7 9 6 1 8 8 7 CS 10 1 1 SDI 7 6 0 13 7 12 0 14 14 SDO 7 Serial Control Interface Timing Diagramme 0 REV. M Page 28 September 1998 AS3502 Devices sold by AUSTRIA MIKRO SYSTEME are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. AUSTRIA MIKRO SYSTEME makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AUSTRIA MIKRO SYSTEME reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with AUSTRIA MIKRO SYSTEME for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by AUSTRIA MIKRO SYSTEME for each application. Copyright (c) 1996-8, Austria Mikro Systeme International AG, Schloss Premstatten, 8141 Unterpremstatten, Austria. Trademarks Registered(R). All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. AUSTRIA MIKRO SYSTEME AG reserves the right to change or discontinue this product without notice. Notes REV. M Page 29 September 1998 |
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